PIM bottleneck resolved -> Up to 11x faster

Recently, as the proportion of memory bandwidth used in research such as artificial intelligence, big data, and life sciences is increasing, active research and development is being conducted on Processing-in-Memory (PIM) semiconductors that place computational units inside the memory.



An international joint research team has solved the bottleneck phenomenon caused by the problem that existing PIM semiconductors must go through a CPU connected to the outside of the PIM semiconductor when communicating while utilizing internal devices.



The Korea Advanced Institute of Science and Technology (KAIST, President Kwang-hyung Lee) announced on the 19th that the research team led by Professor Dong-jun Kim of the Department of Electrical and Electronic Engineering has developed a technique to drastically improve the communication performance of PIM semiconductors through joint research with research teams from Northeastern University, Boston University in the U.S., and Universidad de Murcia in Spain through 'Interconnection Network Architecture Specialized in Collective Communication between PIM Semiconductors'.



Diagram of communication between PIM computational units using PIM-specific interconnect. [Photo = KAIST]



Professor Kim Dong-jun's research team has revealed the limitations of the communication structure between the memory-internal computational devices of existing PIM semiconductors. They proposed a technique to maximize the communication performance of PIM semiconductors by applying an interconnection network structure (a computational device connection structure used in designing large-scale systems including multiple computational devices) that directly interconnects each computational device while making the most of the existing bus structure for data movement within the memory.



Through this, they developed an interconnection network structure specialized for PIM semiconductors that minimizes the intervention of the CPU for communication processing in the computational process for PIM semiconductors and enhances the overall performance and usability of the PIM semiconductor system.



The memory process has the problem that it is difficult to add complex logic, but the network structure developed by Professor Kim Dong-jun's team implemented a cost-effective interconnect in PIM.



This structure is specialized for the collective communication pattern that is widely used in the fields of parallel computing and machine learning. They minimized the main components that generate costs in existing networks by utilizing the determinism characteristic of collective communication that allows each computational device's communication volume and data movement path to be identified in advance.



Existing PIM semiconductors had to go through the CPU to communicate, resulting in significant performance loss. The research team explained that applying a PIM-specific interconnection network improved application performance by up to 11 times compared to existing systems.



Professor Kim Dong-jun said, "Reducing data movement is a key element in all system semiconductors, including PIM." "PIM can improve the performance and efficiency of computing systems, but performance scalability may be limited due to data movement between PIM computational units, limiting its application areas. PIM interconnects can be a solution to this."



This study (title: PIMnet: A Domain-Specific Network for Efficient Collective Communication in Scalable PIM), in which KAIST Department of Electrical Engineering Ph.D. candidate Hyo-jun Son participated as the first author, is scheduled to be presented in March at the 2025 IEEE International Symposium on High Performance Computer Architecture (HPCA 2025), the best international academic conference in the field of computer architecture, held in Las Vegas, Nevada, USA.





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